Job Description
We are looking for a Design Verification Engineer to ensure functional correctness of complex SoCs across AI, GPU, and CPU domains. You’ll develop UVM-based testbenches, run formal and simulation-based verification, and drive coverage closure. Candidates should have 5+ years of experience in digital verification, with strong skills in SystemVerilog, scripting, and tools like VCS or Questa.
Qualifications
BS/MS in Electrical Engineering or Computer Engineering
5+ years in digital verification.
Proficiency in UVM, SystemVerilog, and scripting languages.
Experience with simulation tools (VCS, Questa, etc.)
Key Responsibilities
Develop testbenches and verification plans for complex SoCs.
Use UVM, SystemVerilog, and formal verification tools.
Debug simulation failures and improve coverage metrics.
Collaborate with design and architecture teams to ensure functional correctness.